Apache Labs ANAN-200D (Demo)

Apache Labs ANAN-200D (Demo) SKU: ZAP-ANAN-200D-DEMO


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Apache Labs ANAN-200D SDR (Demo) 

 The ANAN-200D is The most powerful Amateur Radio Transceiver available today, it builds on the very successful OpenHPSDR Hermes and the Apache Labs Angelia designs and offers unprecedented performance/functionality not available in any other HF/6M radio transceiver. 
 There are many firsts that the ANAN-200D/Orion introduces in the HF radio space, like the ANAN-100D this is a dual phase coherent receive system with an extremely robust and sensitive front end and opens up possibilities of applications such as Diversity reception. 
 All major controls and settings such as PTT/Mic/Bias/External reference switching is under software control or automated, hence this is an ideal platform for those who would like a consumer plug & play SDR solution. 
 The ANAN-200D/Orion has been designed keeping in mind advanced applications and uses the largest FPGA in any commercially available Amateur Radio SDR, the current implementation uses less than 35% of the resources and has more than adequate headroom for the future applications.

The ANAN radios define a new level of performance in Amateur Radio transceivers, based on the very popular OpenHPSDR designs,they represent the state-of-the-art in the amateur radio space. 
 Adaptive Predistortion for s Super Clean transmitter on the ANAN The quest for a clean transmitter requires one to either operate in very inefficient Class A mode (at reduced efficiency and power outputs) or invest in a 50v Mosfet design which provides a 10dB improvement in IMD in the best case scenario. 
The ANANs has been designed from the ground up to use modern digital predistortion algorithms to mitigate and reduce the IMD created in the transmitter, 50dB IMD3 has been achieved using Dr Warren Pratt’s (NR0V) revolutionary new WDSP engine which implements adaptive predistortion (PureSignal) winner of the 2014 ARRL Technical Innovation Award. 
Exceptional transmitter output linearity has been achieved, the results are astounding and far superior to any other Amateur radio transceiver available in the market today. IMD Measured on an ANAN-200D (14.2Mhz 100W PEP)
  PureSignal (Adaptive Predistortion) setup and demo on the ANAN-100D, Courtesy Nige, G7CNF Diversity Reception 

 The ANAN-100D and the ANAN-200D can be used for Polarization diversity operations (using two ADCs) to remove QRM and noise far more efficiently than any noise blanker can, Diversity reception is also used to mitigate Faraday Rotation effects and to remove polarization misalignment effects during Rx.
  Diversity Reception, Courtesy Nige G7CNF Software Support 

 • The OpenHPSDR flavours of PowerSDR 
• cuSDR 
• Kiss Konsole 
• John Melton's (G0ORX/N6LYT) android 
• application for The OpenHPSDR hardware 
Apache Labs ANAN-200D SDR (Demo) 
Key Features & Specifications : 
  •  Cyclone IV EP4CGX150 FPGA - 150,000 Logic Elements 
  • Two Independent phase coherent 16 bit LTC2208 Front Ends 
  • Supports multiple Independent receivers covering 160M through 6M 
  • 160M - 6M All mode Transmitter (limited only by Software) 
  • 125dBm Receiver Dynamic Range (All Three Front Ends have identical Dynamic Range) 
  • Supported sampling rates 48/96/192/384 kHz 1.152Mhz of display spectrum with .732 Hz resolution 
  • Software-selectable 31dB input attenuators in 1dB steps Blocking Dynamic Range (ARRL Method) no detectable gain compression below ADC overload 
  • Transmit and receiver image rejection > 110dB 
  • Full duplex operation, any split over entire 160m to 6m range 
  • Extremely Sensitive Receiver, -138dBc MDS @ 14.2MHz, 
  • 500Hz bandwidth 10MHz 100PPB reference oscillator 
  • Ultra low phase noise master clock -149dBc @ 10Khz separation 
  • DUC Transmitter 160M to 6M -48dB IMD3 @ 14.2Mhz, 100W PEP (with Puresignal enabled) 
  • Automatic 10Mhz internal/external clock switching 
  • Software controlled Mic, Mic Bias and PTT 
  • Onboard 128MB Flash 
  • Onboard 32Mbit Synchronous RAM 
  • Industry Standard TCP/IP network Ethernet interface supports static, APIPA or DHCP IP address
  • FPGA code can be updated via the Industry Standard TCP/IP network Ethernet connection 
  • Seven user-configurable open-collector outputs, independently selectable per band and Tx/Rx (for relay control, etc - with sequencing via PC code) 
  • Separate open-collector PTT connection for amplifier control, etc, with sequencer 
  • Four user-configurable 12 bit analogue inputs (for ALC, SWR etc) 
  • Three user-configurable digital inputs (for linear amplifier over temperature, etc) 
  • Low phase noise (-140dBc/Hz @ 1kHz, 14MHz) 122.88MHz master clock, which can be phase-locked to an internal 10MHz 100PPB TCXO or external frequency reference.
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