Apache Labs ANAN-7000DLE MKII -- No Embedded PC
Apache Labs ANAN-7000DLE MKII (No Embedded PC) HF & 6M 100W SDR Transceiver offers top of the line performance is a compact rugged package, it is based on the work of the OpenHPSDR community.
- Using Direct Down Conversion with an ultra-low phase noise clock yields an RMDR of 116dB @ 2Khz separation, this means that close in weak signals will not be masked by the receiver’s phase noise.
- The transmitter specifications are also off the chart, use of a new 16bit DAC with an ultra-low noise clock source results in transmitting phase noise better than any other product available in the market.
- Use of LDMOS drivers and an optimized final Amplifier stage with adaptive Predistortion Algorithm (PureSignal) yields transmit IMD of -68db @ 100W PEP, this is at least 20dB better than any Class A transmitter and over 30dB better than the competition.
- Use of two 16bit phases synchronous ADCs allows for advanced applications such as Diversity reception for ultimate noise mitigation and effects of signal fading.
The new PA board incorporates the following updates over the previous generation:
- Stainless steel chassis and large aluminum heatsink for excellent thermal dissipation and Rx/Tx isolation.
- PA board improvements for higher duty cycle, 100% ICAS duty cycle supported.
- Tx Signal generation redesigned to improve SNR at low power levels.
- Architecture: Direct Sampling DDC/DUC Transceiver
- Interface: Ethernet
- Phase Noise (Clock): -149dB @ 10Khz
- TCXO Stability (Typical): /- .1 PPM
- Modes: CW, SSB, NFM, AM, Digital
- Antenna Ports: Three BNC 50 ohms Software Configurable Ports, Three BNC ADC1 Bypass and Loop in ports, One BNC for RX2
- Frequency Resolution: 1 Hz
- 13.8v DC @ 25A, 3A Receive/25A Transmit
- 10Kg (approx. Weight)
- Dimensions: 384MM (W) x 114MM (H) x 310MM (D) (Not including extrusions)
- Rugged Steel Chassis and Aluminum heatsink with Temperature controlled internal/External (Optional) Fan.
- Receiver Architecture: Direct Down Conversion
- Dual 16 bit Phase Synchronous ADCs
- Independent filter banks for each ADC
- 6M LNAs
- Frequency Coverage: 9Khz to 60Mhz
- Attenuator: 1-30dB step attenuator
- Reciprocal Mixing Dynamic Range (RMDR): 116dB @ 2Khz offset
- Receiver Phase noise: -149dB @ 10Khz
- Image rejection: 90dB
- Hardware support for 7 independent receivers assignable to either ADC
- Transmitter Architecture: Direct Up Conversion
- DAC Resolution: 16 bit
- RF Output Power: 100W PEP SSB, FM, RTTY, Digital; 1-30W AM, 100W CW
- IMD: IMD3 typically -68dB below PEP @ 100W output on 20M
- Harmonics: Typically better than -43dBc on HF and -60dBc on 6M
- Carrier and Opposite Sideband Suppression: Better than -80dBc
- Transverter IF Output: 0db to 15dB
- RCA Line In, Digital Inputs, PTT in, PTT Out
- DB9 Seven Software Configurable Open Collector Outputs
- SMA XVTR, 10Mhz reference Input
- 3.25mm Barrel Mic, CW Key, Headphones and two 6.25mm Speaker Outputs
- RJ45 Ethernet LAN Connector